1. Field of the Invention
The present invention relates to a die bond film that is used to adhere, onto a semiconductor element such as a semiconductor chip that is electrically connected to an adherend such as a lead frame with a bonding wire, another semiconductor element. The present invention also relates to a dicing die bond film in which the die bond film and a dicing film are laminated. Further, the present invention relates to a semiconductor device that is manufactured using the die bond film or the dicing die bond film.
2. Description of the Related Art
Demands for attaining higher density and higher integration of a semiconductor device have been becoming stronger corresponding to enhanced functionality of electronic equipment, and the capacity and the density of semiconductor packages have been increasing in recent years. In order to answer to this demand, for example, there has been investigated a method of implementing a smaller size, smaller thickness, and larger capacity semiconductor package by laminating, onto a semiconductor chip, another semiconductor chip in multiple stages. A wire bonding method using a bonding wire is normally broadly adopted as a method of electrically connecting a semiconductor chip and a substrate in such semiconductor package.
When die-bonding, onto a semiconductor chip that is loaded on a substrate, another semiconductor chip, it is necessary to die-bond the other semiconductor chip while avoiding an electrode pad for wire bonding on the semiconductor chip. Because of this, there is adopted a method of securing a region where a semiconductor chip 102 and a substrate 101 are electrically connected by a bonding wire 105 using another semiconductor chip 103 having a smaller area than that of the semiconductor chip 102 loaded on the substrate 101 with an adhesive 104 or the like as shown in FIG. 8A, for example (refer to FIG. 5 of Japanese Patent Application Laid-Open No. 2001-308262).
Further, when laminating a semiconductor chip 103 having a similar area as that of the semiconductor chip 102 loaded on the substrate 101 as shown in FIG. 8B, there is adopted a method of having a spacer 106 whose area is smaller than that of the semiconductor chip 102 between the semiconductor chip 102 and the semiconductor chip 103 (refer to FIG. 4 of Japanese Patent Application Laid-Open No. 2001-308262). With this configuration, the semiconductor chip 103 is prevented from overlapping the bonding wire 105 that electrically connects the semiconductor chip 102 and the substrate 101. However, a new step of providing the spacer 106 onto the semiconductor chip 102 is necessary in this method. It is also necessary to make the thickness of the spacer 106 sufficiently large for preventing the semiconductor chip 103 from contacting the bonding wire 105. As a result, this method is unsuitable for attaining a thinner semiconductor device.
In order to solve such problems, there is disclosed a method of forming an adhesive layer for fixing made of a die bond resin by applying the die bond resin to the semiconductor chip 102 that is electrically connected to the substrate 101 by the bonding wire 105 such that a sufficient distance can be secured between the semiconductor chip 102 and the semiconductor chip 103, and then laminating the semiconductor chip 103 (refer to FIG. 1 of Japanese Patent Application Laid-Open No. 2001-308262). However, the backside of the semiconductor chip 103 and the bonding wire 105 may contact with each other when die-bonding the semiconductor chip 103 onto the adhesive layer for fixing and the bonding wire 105 may deform or cut. As a result, it becomes difficult to maintain electrical connection between the substrate 101 and the semiconductor chip 102, and the yield may decrease.